VHDL 설계 언어 실습(문법적용)리포트 > 공학/기술 26페이지 
◆ logic1
1.소스
library ieee;
use ieee.std_logic_1164.all;
entity logic1 is
port(a,b,c :in bit;
y :out bit);
end logic1;
architecture sample of logic1 is
signal w, x : bit;
begin
no1: proces..
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